The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method suitable for manufacturing a p-channel MOS transistor.
To reduce signal propagation delay times in the gate of an n-channel MOS transistor, a low-resistance refractory metal such as tungsten, or a silicide of such a metal, is often used in the gate. However, since there is a problem concerning the interface between such materials and a gate oxide layer formed of silicon oxide, it is common to form the gate of a multi-layer structure comprising a polysilicon film formed over the gate oxide film, and a thin film of the refractory metal, or the silicide of the metal, formed over the polysilicon film. In this case, an n-type impurity is usually added to the polysilicon film by a POCl.sub.3 diffusion method, to make the film electrically conductive.
To satisfy recent demands for higher levels of integration, higher operating speeds, and lower power dissipations, there is a trend toward using complementary MOS transistors instead of n-channel MOS transistors alone. As is well known, complementary transistors consist of a pair of an n-channel MOS transistor and a p-channel MOS transistor. For the gate electrodes of both the n-channel MOS transistor and the p-channel MOS transistor, it is common practice to use a polysilicon film to which an n-type impurity has been diffused, between a gate oxide film and a thin film of a refractory metal or a silicide of a refractory metal.
A cross-section through an element of this structure is shown in FIG. 1. This figure shows the structure of a CMOS inverter circuit in which an n-type impurity layer 1801 acting as the source region of an n-channel MOS transistor and an n-type impurity layer 1803 acting as a drain region of the same transistor are formed in the surface of a p-type semiconductor substrate 1800, with a channel portion 1802 therebetween. In addition, a p-type impurity layer 1811 acting as the source region of a p-channel MOS transistor and a p-type impurity layer 1813 acting as the drain region of the same transistor are formed in an n-well 1820, with a p-channel portion 1812 therebetween. An inter-layer insulating film 1840 is formed over the semiconductor substrate 1800. To provide a gate electrode for the n-channel MOS transistor, a polysilicon film 1805 is formed on a gate oxide film 1804, and a metal silicide film 1806 is formed on the polysilicon film 1805. In the same way, to provide a gate electrode for the p-channel MOS transistor, a gate oxide film 1814, a polysilicon film 1815, and a metal silicide film 1816 are formed in sequence. The two polysilicon films 1805 and 1815 are implanted with a high dosage of at least 10.sup.21 atoms/cm.sup.3 of, for example, arsenic, as an n-type impurity. The p-type impurity layer 1811 (1822) (source) is connected to a power source (not shown in the figure) by an interconnection/electrode 1832 made of a material such as aluminum, and an n-type impurity layer 1823 (source) is connected to the power source by an interconnection/electrode 1833. The n-type impurity layer 1803 (drain) of the n-channel MOS transistor and the p-type impurity layer 1813 (drain) of the p-channel MOS transistor are connected together by wiring 1821 that transfers an inverter output 1834 to an external device (not shown in the figure). Inverter inputs come from an interconnection 1831 are supplied to the metal silicide film 1806 and the polysilicon film 1805 acting as the gate electrode of the n-channel MOS transistor and the metal silicide film 1816 and the polysilicon film 1815 acting as the gate electrode of the p-channel MOS transistor.
In order to improve the I/O characteristics and operating speeds of this CMOS inverter, it is necessary to control the threshold voltages of the n-channel and p-channel MOS transistors to a high degree of accuracy. Some of the phenomena that affect threshold voltages are the work functions of the materials of the gate electrode and the thickness of its oxide film, the profile of the impurity layer, and the interface charge. To increase operating speeds, it is best to have a threshold voltage close to zero. But to allow room for noise detection, it is preferable to have a threshold voltage that is far from zero. Therefore, it is common practice to treat the threshold voltages of the two transistors as a pair and, for example, set the threshold voltage of the n-channel MOS transistor to approximately 0.8 V, and that of the p-channel MOS transistor to approximately -0.8 V. However, as elements get smaller, the distances between the source and drain become shorter, making punch-through current more likely to occur, so the construction described below has become necessary.
As shown in the cross-section through the structure of a p-channel MOS transistor in FIG. 2, a high-concentration, n-type punch-through current suppression layer 2704 is formed in a channel region between p-type impurity layers 2703 and 2702.
In an n-channel MOS transistor, there would be no bad effect if an n-type impurity were implanted into a polysilicon film 2707 that forms a gate electrode. However, if an n-type impurity is implanted into such a polysilicon film 2707 of the p-channel MOS transistor, the work function of the gate electrode of the p-channel structure will become greater than in the case when a p-type impurity is implanted, and the threshold voltage will move further away from zero from -0.8 V (for p-type impurity implanted polysilicon) to, for instance, -2.0 V, hindering any increase in operating speed. To prevent this, a p-type impurity must be implanted as a counter-dose into the region below a gate oxide film 2706, reducing the concentration of n-type impurity in this portion. To illustrate what happens in this case, the portion enclosed in the box B in FIG. 2 is enlarged in FIG. 3, and the variation of impurity concentration in the depthwise direction is shown in FIG. 4. As shown in FIG. 3, a carrier depletion layer 2803 is generated between the n-type punch-through current suppression layer 2704 and the p-type impurity layer 2702, and an n-type low-concentration counter-dose region 2705 is formed below the gate oxide film 2706. This reduces the impurity concentration, bringing it closer to the boundary line with the gate oxide film, as shown in FIG. 4 (2830).
However, as the impurity concentration decreases in this way, as shown by a reference numeral 2820 in FIG. 4, a punch-through current is more likely to be generated. Thus, there are conflicting demands that the threshold voltage should be both near zero to increase operating speeds, and be large enough to prevent the occurrence of punch-through currents. In order to satisfy both demands, the inventors have proposed (in Japanese No. 1513852) a structure wherein the polysilicon film 2707 of the p-channel MOS transistor is made different from the polysilicon film of the n-channel MOS transistor, by the implantation of a p-type impurity. A cross-section through a device having a polysilicon film of this structure is shown in FIG. 5.
In the same way as the device of FIG. 1, n-type impurity layers 2101 (source) and 2103 (drain) of an n-channel MOS transistor are formed in the surface of a p-type semiconductor substrate 2100, and p-type impurity layers 2111 (source) and 2113 (drain) of a p-channel MOS transistor are formed in an n-well 2120, but this device differs from that of FIG. 1 in that a p-type impurity is implanted into a polysilicon film 2115 that forms part of a gate electrode on the p-channel MOS transistor side. In addition, the n-type impurity layer 2103 of the n-channel MOS transistor and the p-type impurity layer 2113 of the p-channel MOS transistor are connected by a polysilicon layer, but a p-type impurity is implanted on a p-type impurity layer side 2124 thereof, and an n-type impurity is implanted on an n-type impurity layer side 2123 thereof.
With this structure, if a p-type impurity is implanted into the polysilicon film 2115 on the p-channel MOS transistor side, there is no occurrence of the phenomenon described above whereby the implantation of an n-type impurity tends to cause a change in the work function that moves the threshold voltage far away from zero. Therefore, there is no need to reduce the n-type impurity concentration in a counter-dose region below a gate oxide film 2114 that is part of a punch-through current suppression layer 2112 thereof (It is necessary to implant a small amount of impurity in order to control the fine V.sub.th. This both keeps the threshold voltage close to zero, increases the operating speed, and prevents the generation of a punch-through current.
However, this conventional method of manufacturing a semiconductor device has the problem that the threshold voltage of the p-channel MOS transistor can deviate wildly from its value set at the design stage, making it impossible to control with a high degree of accuracy. The cause of this deviation will now be described with reference to FIG. 6. This figure shows the stage in the manufacture after the gate oxide film 2114 and a polysilicon film that has not yet had any p-type impurity implanted into it are formed on the n-well 2120 formed in the p-type semiconductor substrate 2100, and after an impurity has been added to the punch-through current suppression layer 2112, but before the high-concentration p-type impurity layers 2111 (source, not shown in the figure) and 2113 (drain) have been formed, and before a polysilicon film 2211 has been patterned.
In this case, assume that elemental boron ions (B.sup.+) are the most suitable p-type impurity to be implanted into the polysilicon film 2211. Since the atomic number of boron is 5, the ion implantation obstruction capacity (stopping power) of the polysilicon film 2211 with respect to boron is substantially lower than that for other impurities such as phosphorous (atomic number 15) and arsenic (atomic number 33). Therefore, the accelerating voltage required for implanting the boron ions will inevitably be very small, on the order of, for example, 20 keV. However, since such an accelerating voltage is too small to ensure that the boron ions are drawn stably out of the ion source, it is difficult to control the accelerating voltage in such a way that it is kept small enough that the ions penetrate the polysilicon film 2211 but are not implanted into the channel portions, and that they are implanted to the optimal depth.
One method of solving the problem of the too-small accelerating voltage is to use boron fluoride (BF.sub.2.sup.+) ions, which enables implantation at a higher accelerating voltage while reducing the implantation depth to approximately 1/5 of the depth achieved by boron ions. However, since molecular boron fluoride ions tend to separate into more stable forms of boron ions and fluorine ions, in practice, this method causes about the same sort of problem as that of the implantation of boron ions alone. (Refer to 89 IEDM Technical Digest No. 17-1, Frank K. Baker et al. and No. 17-2, J. M. Sung et al.) Therefore, it is difficult to control the implantation depth of the boron ions to such a high degree of accuracy that they stop within the polysilicon film 2211.
Another problem concerns the crystallization of the polysilicon film 2211. As shown in FIG. 6, grains of the polysilicon film above the p-type impurity layer 2113 grow irregularly, but the crystals above the gate oxide film 2114 grow with their axes aligned. As a result, the boron ions stop within the polysilicon film 2211 above the region destined to become the p-type impurity layer 2113, as shown by the arrow 2201, but many of those that penetrate above the gate oxide film 2114 travel as far as a channel region formed by the punch-through current suppression layer 2112, as shown by the arrow 2202, causing one reason for variations in threshold voltage.